1. Field of the Invention
The present invention relates to a data processing device (microprocessing unit), more particularly, to a data processing device for a variable length instruction system using pipeline processing.
2. Description of the Related Art
Conventionally, in a general data processing device, considerable time is spent reading our data from memory cells to bit lines, as each of the bit lines has a large load capacity. Therefore, it has been impossible to transfer a next instruction string following an instruction beginning into an instruction decoder in a short time, so that a delay time becomes large and an instruction processing speed cannot be decreased.
In consideration of the above, a data processing device, which can decrease the time required for reading out data from memory cells, has been studied and proposed as related art. A data processing device which can decrease the time for reading out data from memory cells comprises a memory management unit, an instruction buffer (instruction buffer memory), and an instruction decoder. In this data processing device, two word lines (a first word line and a second word line) are provided for each single memory cell in the instruction buffer, and data are read out to corresponding bit lines. The first word line is connected to a first read pointer, the second word line is connected to a second read pointer, and instruction bit strings designated by the first and second read pointers are read out to the bit lines. Note, in the data processing device according to the related art, memory cells which store an instruction bit string following the next instruction beginning are only specified, after receiving an instruction length notification signal output from the instruction decoder.
Further, the data are read out from the specified memory cells to the bit lines, and the data are latched and transferred to the instruction decoder.
As described above, in the general data processing device, an instruction processing speed cannot be decreased, as a load capacity of each bit line is quite large. On the other hand, in the data processing device according to the related art, two bit lines and two word lines are required, furthermore, transistors connected to respective word lines are also required, and thus a large scale integration, a small size, and a low cost cannot be realized.
Incidentally, in a data processing device, pipeline processing has been used in order to realize a high speed operation. In recent years, this pipeline processing is also used in a monolithic microprocessor such as a 32-bit microprocessing unit using a TRON (The Realtime Operating system Nucleus) architecture. In pipeline processing, a single instruction processing has been divided into several processings (several pipeline stages), and a plurality of pipeline stages have been carried out in parallel, so that high speed processing can be realized.
Nevertheless, in a variable length instruction system using pipeline processing, the length of an instruction cannot be known and a starting point of the newt instruction cannot be discriminated before decoding the instruction. Namely, in the variable length instruction system, a starting point of a next instruction can only be discriminated after decoding the instruction, and thus an instruction processing time is determined in accordance with the time taken to decode the instruction, discriminate the instruction length (instruction word length), and read out the next instruction. For example, even if a processing time of a single pipeline stage is shortened, a start of decoding (or processing) the next instruction is still slow, so instruction processing speed cannot be reduced. Therefore, it is pressingly required to greatly increase a transition speed (or shorten a transition time) for discriminating an instruction length and read out a next instruction. Furthermore, in a monolithic microprocessor such a device formed in a single semiconductor body, it is desired to minimize a chip size to reduce production cost, decrease power consumption, and improve production yield thereof.